// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 .
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : apb_interface.sv
// Author        : 
// Created On    : 2022-08-25 15:10
// Last Modified : 
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

`ifndef __APB_INTERFACE_SV__
`define __APB_INTERFACE_SV__

`timescale 1ns/1ps

interface apb_interface(input pclk, presetn);

	logic [47:0]    paddr;
    logic [31:0]    prdata;
    logic [31:0]    pwdata;
    logic           psel;
    logic           penable;
    logic           pwrite;
    logic           pready;
    logic           pslverr;
    logic  [3:0]    pstrb;

    clocking master_cb @(posedge pclk);
        default input #1ps output #1ps;
        output  pwrite;
        output  paddr;
        output  pwdata;
        output  psel;
        output  penable;
        output  pstrb;

        input   pready;
        input   prdata;
        input   pslverr;
	endclocking : master_cb
	modport pkt_master (clocking master_cb);

	clocking slave_cb @(posedge pclk);
		default input #1ps output #1ps;
        input  pwrite;
        input  paddr;
        input  pwdata;
        input  psel;
        input  penable;
        input  pstrb;

        output pready;
        output prdata;
        output pslverr;
	endclocking : slave_cb
	modport pkt_slave (clocking slave_cb);

	clocking mon_cb @(posedge pclk);
		default input #1ps output #1ps;
        input  pwrite;
        input  paddr;
        input  pwdata;
        input  psel;
        input  penable;
        input  pstrb;

        input  pready;
        input  prdata;
        input  pslverr;
	endclocking : mon_cb
	modport pkt_mon (clocking mon_cb);

endinterface

`endif
